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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10522655 B1

PDFFull Text
Date of Patent:
Dec. 31, 2019

Filed:

Sep. 21, 2017

Differential sg/eg spacer integration with equivalent nfet/pfet spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage eg device on fdsoi

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

George Robert Mulfinger, Wilton, NY (US);

Ryan Sporer, Mechanicsville, NY (US);

Rick J. Carter, Saratoga Springs, NY (US);

Peter Baars, Dresden, DE;

Hans-Jürgen Thees, Dresden, DE;

Jan Höntschel, Dresden, DE;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:

Ditthavong & Steiner, P.C.

Primary Examiner:

Raj R Gupta

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6656 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 21/84 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H01L 29/7838 (2013.01); H01L 29/0847 (2013.01);
Abstract

A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

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