The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Aug. 14, 2017
Applicant:

Maxpower Semiconductor, Inc., San Jose, CA (US);

Inventors:

Richard A. Blanchard, Los Altos, CA (US);

Mohamed N. Darwish, Campbell, CA (US);

Jun Zeng, Torrance, CA (US);

Assignee:

MAXPOWER SEMICONDUCTOR, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 21/04 (2006.01); H01L 21/265 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66068 (2013.01); H01L 21/047 (2013.01); H01L 21/26586 (2013.01); H01L 29/0623 (2013.01); H01L 29/0634 (2013.01); H01L 29/0878 (2013.01); H01L 29/1037 (2013.01); H01L 29/1095 (2013.01); H01L 29/16 (2013.01); H01L 29/407 (2013.01); H01L 29/42368 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01); H01L 29/1608 (2013.01); H01L 29/41766 (2013.01);
Abstract

In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.


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