The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Jan. 08, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Yu-Chang Lin, Hsinchu, TW;

Shih-Hsiang Chiu, New Taipei, TW;

Tien-Shun Chang, New Taipei, TW;

Chun-Feng Nieh, Hsinchu, TW;

Huicheng Chang, Tainan, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/3115 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/02164 (2013.01); H01L 21/31155 (2013.01); H01L 21/823878 (2013.01); H01L 29/0653 (2013.01);
Abstract

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.


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