The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Nov. 24, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chao-Hsun Wang, Taoyuan, TW;

Kuo-Yi Chao, Hsinchu, TW;

Rueijer Lin, Hsinchu, TW;

Chen-Yuan Kao, Zhudong Township, Hsinchu County, TW;

Mei-Yun Wang, Chupei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 23/535 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/76897 (2013.01); H01L 23/535 (2013.01); H01L 29/41791 (2013.01); H01L 29/456 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure includes a gate electrode layer formed over the gate dielectric later and a gate contact structure formed over the gate electrode layer. The gate contact structure includes a first conductive layer formed over the gate electrode layer, a barrier layer formed over the first conductive layer and a second conductive layer over the barrier layer. The second conductive layer is electrically connected to the gate electrode layer by the first conductive layer.


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