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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10424655 B1

PDFFull Text
Date of Patent:
Sep. 24, 2019

Filed:

Dec. 15, 2017

Dual gate ldmos and a process of forming thereof

Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Ming Li, Singapore, SG;

Jeoung Mo Koo, Singapore, SG;

Raj Verma Purakh, Singapore, SG;

Assignee:

GLOBALFOUNDRIES SINGAPORE PTE. LTD., Singapore, SG;

Attorney:

Thompson Hine LLP

Primary Examiner:

Robert G Bachner

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/28 (2006.01); H01L 29/36 (2006.01); H01L 21/762 (2006.01); H01L 21/66 (2006.01); H01L 29/40 (2006.01); H01L 27/092 (2006.01); H01L 21/3105 (2006.01); H01L 21/266 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66681 (2013.01); H01L 21/02238 (2013.01); H01L 21/26513 (2013.01); H01L 21/28035 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01); H01L 29/0865 (2013.01); H01L 29/0882 (2013.01); H01L 29/1095 (2013.01); H01L 29/36 (2013.01); H01L 29/42368 (2013.01); H01L 29/42376 (2013.01); H01L 29/4916 (2013.01); H01L 29/7816 (2013.01); H01L 21/266 (2013.01); H01L 21/31053 (2013.01); H01L 21/32137 (2013.01); H01L 22/26 (2013.01); H01L 27/092 (2013.01); H01L 29/063 (2013.01); H01L 29/402 (2013.01);
Abstract

A method for forming a high voltage device is disclosed. The method comprises providing a substrate defined with a high voltage device region. A device well is formed to encompass the high voltage device region. A drift region is formed within the device well. A body well is formed within the device well adjacent to the drift region. A variable thickness gate dielectric is formed on the substrate. Forming the variable thickness gate dielectric comprises patterned a sacrificial polysilicon layer and oxidizing the patterned sacrificial polysilicon layer to define a thick gate oxide having sloped sidewalls. A gate electrode is formed on the variable thickness gate dielectric, wherein the gate electrode partially overlaps the thick gate oxide. A first and a second source/drain (S/D) region is formed adjacent to first and second sides of the variable thickness gate dielectric.

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