The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Dec. 22, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Feras Eid, Chandler, AZ (US);

Nader N. Abazarnia, Chandler, AZ (US);

Johanna M. Swan, Scottsdale, AZ (US);

Taesha D. Beasley, Chandler, AZ (US);

Sasha N. Oster, Chandler, AZ (US);

Tannaz Harirchian, Chandler, AZ (US);

Shawna M. Liff, Scottsdale, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/373 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/367 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/565 (2013.01); H01L 23/3677 (2013.01); H01L 23/3736 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/3121 (2013.01); H01L 23/3128 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06575 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/0715 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/1206 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/1436 (2013.01);
Abstract

An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.


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