The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Jul. 31, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Elijah V. Karpov, Santa Clara, CA (US);

Prashant Majhi, San Jose, CA (US);

Roza Kotlyar, Portland, OR (US);

Niloy Mukherjee, Portland, OR (US);

Charles C. Kuo, Hillsboro, OR (US);

Uday Shah, Portland, OR (US);

Ravi Pillarisetty, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/07 (2006.01); H01L 29/02 (2006.01); H01L 29/49 (2006.01); H01L 27/12 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 27/0705 (2013.01); H01L 27/1225 (2013.01); H01L 27/2436 (2013.01); H01L 29/02 (2013.01); H01L 29/4908 (2013.01); H01L 29/78603 (2013.01); H01L 29/78642 (2013.01); H01L 45/04 (2013.01); H01L 45/1206 (2013.01); H01L 45/1233 (2013.01); H01L 45/145 (2013.01); H01L 45/146 (2013.01);
Abstract

A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.


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