The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2019

Filed:

Aug. 06, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yun-Tai Shih, Lugang Township, TW;

Kuan-Ming Pan, Hsinchu, TW;

Jeng-Hao Lin, Chubei, TW;

I-Shi Wang, Sanxia Township, TW;

Jui-Mu Cho, Chupei, TW;

Ching-Hou Su, Hsinchu, TW;

Chyi-Tsong Ni, Hsinchu, TW;

Wun-Kai Tsai, Huwei Township, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/544 (2006.01); H01L 21/67 (2006.01); H01L 21/68 (2006.01);
U.S. Cl.
CPC ...
H01L 24/75 (2013.01); H01L 21/67092 (2013.01); H01L 21/681 (2013.01); H01L 23/544 (2013.01); H01L 21/68 (2013.01); H01L 21/682 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/75703 (2013.01); H01L 2224/75753 (2013.01); H01L 2224/75901 (2013.01); Y10T 29/49 (2015.01); Y10T 29/49002 (2015.01); Y10T 29/49131 (2015.01); Y10T 29/49764 (2015.01); Y10T 29/53022 (2015.01);
Abstract

An apparatus includes a bonding system configured to bond at least two wafers. The bonding system has a flag-out mechanism configured to remove a plurality of flags from an area between the at least two wafers. The apparatus also includes sensors configured to detect data related to a flag-out condition of the flags of the plurality of flag. The apparatus further includes at least one processor configured to receive inputs from the sensors, to calculate at least one value related to flag-out timing, and to drive a display indicating an alignment of the at least two wafers.


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