The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

May. 23, 2018
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Inventors:

Ji-Min Lin, Taichung, TW;

Yi-Wei Chen, Taichung, TW;

Tsun-Min Cheng, Changhua County, TW;

Pin-Hong Chen, Tainan, TW;

Chih-Chien Liu, Taipei, TW;

Chun-Chieh Chiu, Keelung, TW;

Tzu-Chieh Chen, Pingtung County, TW;

Chih-Chieh Tsai, Kaohsiung, TW;

Yi-An Huang, New Taipei, TW;

Kai-Jiun Chang, Taoyuan, TW;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, unknown;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 29/43 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4958 (2013.01); H01L 21/28035 (2013.01); H01L 21/28044 (2013.01); H01L 21/823437 (2013.01); H01L 29/4232 (2013.01); H01L 29/435 (2013.01); H01L 29/4916 (2013.01); H01L 29/4941 (2013.01);
Abstract

A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a metal silicon nitride layer on the silicon layer; forming a stress layer on the metal silicon nitride layer; performing a thermal treatment process; removing the stress layer; forming a conductive layer on the metal silicon nitride layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.


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