The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Jan. 18, 2016
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Martin Mischitz, Wernberg, AT;

Markus Heinrici, Villach, AT;

Michael Roesner, Villach, AT;

Oliver Hellmund, Neubiberg, DE;

Caterina Travan, Villach, AT;

Manfred Schneegans, Vaterstetten, DE;

Peter Irsigler, Obernberg am Inn, AT;

Friedrich Kroener, Villach, AT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 24/03 (2013.01); H01L 24/94 (2013.01); H01L 2224/03312 (2013.01); H01L 2224/03318 (2013.01); H01L 2224/03332 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03622 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/29111 (2013.01); H01L 2224/29116 (2013.01);
Abstract

According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.


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