The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2019
Filed:
Apr. 03, 2018
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Shih Pei Chou, Tainan, TW;
Hung-Wen Hsu, Tainan, TW;
Ching-Chung Su, Tainan, TW;
Chun-Han Tsao, New Taipei, TW;
Chia-Chieh Lin, Kaohsiung, TW;
Shu-Ting Tsai, Kaohsiung, TW;
Jiech-Fun Lu, Madou Township, TW;
Shih-Chang Liu, Alian Township, TW;
Yeur-Luen Tu, Taichung, TW;
Chia-Shiung Tsai, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.