The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2019
Filed:
Jan. 10, 2018
Powertech Technology Inc., Hukou Township, Hsinchu County, TW;
Ming-Chih Chen, Hukou Township, Hsinchu County, TW;
Hung-Hsin Hsu, Hukou Township, Hsinchu County, TW;
Yuan-Fu Lan, Hukou Township, Hsinchu County, TW;
Chi-An Wang, Hukou Township, Hsinchu County, TW;
Hsien-Wen Hsu, Hukou Township, Hsinchu County, TW;
POWERTECH TECHNOLOGY INC., Hukou Township, Hsinchu County, TW;
Abstract
A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.