The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Nov. 08, 2017
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Wei Si, Singapore, SG;

Zeng Wang, Singapore, SG;

Jeoung Mo Koo, Singapore, SG;

Raj Verma Purakh, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 27/11517 (2017.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); G11C 16/045 (2013.01); G11C 16/0416 (2013.01); G11C 16/34 (2013.01); H01L 21/28035 (2013.01); H01L 27/11517 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01);
Abstract

Device and method of forming a non-volatile memory (NVM) device are disclosed. The NVM device includes NVM cells disposed on a substrate in a device region. The NVM cell includes a floating gate (FG) with first and second FG sidewalls disposed on the substrate and an intergate dielectric layer disposed over the FG and substrate. Re-entrants are disposed at corners of the intergate dielectric which are filled by dielectric re-entrant spacers. An access gate (AG) with first and second AG sidewalls is disposed on the substrate adjacent to the FG such that the second AG sidewall is adjacent to a first FG sidewall and separated by the intergate dielectric layer and the re-entrant spacers prevent AG from filling the re-entrants. A first source/drain (S/D) region is disposed in the substrate adjacent to the first AG sidewall and a second S/D region is disposed in the substrate adjacent to the second FG sidewall.


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