The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Sep. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yi Xu, Folsom, CA (US);

Florence Pon, Folsom, CA (US);

Yong She, Songjiang, CN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/112 (2006.01); G06F 17/50 (2006.01); H01L 21/768 (2006.01); H01L 23/525 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1128 (2013.01); G06F 17/505 (2013.01); G06F 17/5068 (2013.01); H01L 21/768 (2013.01); H01L 23/5252 (2013.01); H01L 27/11206 (2013.01); H03K 19/1778 (2013.01); H03K 19/17736 (2013.01); H03K 19/17748 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01);
Abstract

An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.


Find Patent Forward Citations

Loading…