The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Feb. 10, 2015
Applicant:

Shin-etsu Handotai Co., Ltd., Tokyo, JP;

Inventors:

Kazunori Hagimoto, Takasaki, JP;

Masaru Shinomiya, Annaka, JP;

Keitaro Tsuchiya, Takasaki, JP;

Hirokazu Goto, Minato-ku, JP;

Ken Sato, Miyoshi-machi, JP;

Hiroshi Shikauchi, Niiza, JP;

Shoichi Kobayashi, Jyoetsu, JP;

Hirotaka Kurimoto, Jyoetsu, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/32 (2006.01); H01L 21/02 (2006.01); C30B 25/18 (2006.01); C30B 29/40 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0254 (2013.01); C30B 25/183 (2013.01); C30B 29/403 (2013.01); H01L 21/0243 (2013.01); H01L 21/02378 (2013.01); H01L 21/02381 (2013.01); H01L 21/02458 (2013.01); H01L 29/2003 (2013.01);
Abstract

A method of manufacturing an epitaxial wafer having an epitaxial layer on a silicon-based substrate, the method of manufacturing the epitaxial wafer including epitaxially growing a semiconductor layer on the silicon-based substrate after applying terrace processing to an outer peripheral portion of the silicon-based substrate. As a result, the method of manufacturing the epitaxial wafer having the epitaxial layer on the silicon-based substrate in which an epitaxial wafer which is completely free from cracks can be obtained, is provided.


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