The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Jul. 10, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

David Daycock, Boise, ID (US);

Richard J. Hill, Boise, ID (US);

Christopher Larsen, Boise, ID (US);

Woohee Kim, Meridian, ID (US);

Justin B. Dorhout, Boise, ID (US);

Brett D. Lowe, Boise, ID (US);

John D. Hopkins, Meridian, ID (US);

Qian Tao, Boise, ID (US);

Barbara L. Casey, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 21/28 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28282 (2013.01); H01L 29/1037 (2013.01); H01L 29/4234 (2013.01); H01L 29/7926 (2013.01);
Abstract

Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.


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