The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2019
Filed:
Sep. 05, 2017
Globalfoundries Inc., Grand Cayman, KY;
Ruilong Xie, Schenectady, NY (US);
Julien Frougier, Albany, NY (US);
Min Gyu Sung, Latham, NY (US);
Edward Joseph Nowak, Shelburne, VT (US);
Nigel G. Cave, Saratoga Springs, NY (US);
Lars Liebmann, Mechanicville, NY (US);
Daniel Chanemougame, Niskayuna, NY (US);
Andreas Knorr, Saratoga Springs, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.