The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
Mar. 27, 2018
Powertech Technology Inc., Hsinchu County, TW;
Kun-Yung Huang, Hsinchu County, TW;
Chi-Liang Pan, Hsinchu County, TW;
Jing-Hua Cheng, Hsinchu County, TW;
Bin-Hui Tseng, Hsinchu County, TW;
Powertech Technology Inc., Hsinchu County, TW;
Abstract
A semiconductor package including a chip stack, at least one conductive wire, a first insulating encapsulant, a second insulating encapsulant, and a redistribution layer is provided, and a manufacturing method thereof is also provided. The chip stack includes semiconductor chips stacked on top of each other. Each semiconductor chip has an active surface that has at least one bonding region, and each bonding region is exposed by the chip stack. The conductive wire is correspondingly disposed on the bonding region. The first insulating encapsulant encapsulates the bonding region and the conductive wire. At least a portion of each conductive wire is exposed from the first insulating encapsulant. The second insulating encapsulant encapsulates the chip stack and the first insulating encapsulant. The first insulating encapsulant is exposed from the second insulating encapsulant. The redistribution layer is disposed on the first and second insulating encapsulant and electrically coupled to the conductive wire.