The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
Nov. 30, 2017
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Chih-Hao Chang, Hsinchu County, TW;
Hsin-Hung Liao, Taipei, TW;
Hao-Yi Tsai, Hsinchu, TW;
Chien-Ling Hwang, Hsinchu, TW;
Wei-Sen Chang, Kinmen County, TW;
Tsung-Hsien Chiang, Hsinchu, TW;
Tin-Hao Kuo, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts. A plurality of conductive terminals are formed on the surfaces of the conductive posts exposed by the openings.