The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
May. 11, 2017
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Yung-Sung Yen, New Taipei, TW;
Yu-Hsun Chen, Taichung, TW;
Chen-Hau Wu, New Taipei, TW;
Chun-Kuang Chen, Hsinchu County, TW;
Ta-Ching Yu, Hsinchu County, TW;
Ken-Hsien Hsieh, Taipei, TW;
Ming-Jhih Kuo, Hsinchu County, TW;
Ru-Gun Liu, Hsinchu County, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.