The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Sep. 19, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Cheng-Ying Ho, Minxiong Township, TW;

Jeng-Shyan Lin, Tainan, TW;

Wen-I Hsu, Tainan, TW;

Feng-Chi Hung, Chu-Bei, TW;

Dun-Nian Yaung, Taipei, TW;

Ying-Ling Tsai, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/7681 (2013.01); H01L 21/76802 (2013.01); H01L 21/76805 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 24/02 (2013.01); H01L 24/04 (2013.01); H01L 24/24 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 24/83 (2013.01); H01L 24/91 (2013.01); H01L 25/50 (2013.01); H01L 24/48 (2013.01); H01L 24/80 (2013.01); H01L 24/82 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/2405 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/24147 (2013.01); H01L 2224/32146 (2013.01); H01L 2224/451 (2013.01); H01L 2224/48463 (2013.01); H01L 2224/73227 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/82031 (2013.01); H01L 2224/92 (2013.01); H01L 2224/9202 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/00014 (2013.01);
Abstract

A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.


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