The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2019
Filed:
Dec. 27, 2017
United Microelectronics Corp., Hsin-Chu, TW;
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;
Chien-Ting Ho, Taichung, TW;
Shih-Fang Tzou, Tainan, TW;
Chun-Yuan Wu, Yun-Lin County, TW;
Li-Wei Feng, Kaohsiung, TW;
Yu-Chieh Lin, Kaohsiung, TW;
Ying-Chiao Wang, Changhua County, TW;
Tsung-Ying Tsai, Kaohsiung, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;
Abstract
The present invention proposes a method of manufacturing a semiconductor device, which includes the steps of providing a substrate with a memory region and a logic region, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-K dielectric layer on sidewalls of bit lines, forming a doped silicon layer in the storage node regions between bit lines, wherein the top surface of doped silicon layer is lower than the top surface of bit line, forming a second low-K dielectric layer on sidewalls of storage node regions, and filling up storage node regions with metal plugs.