The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Dec. 18, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Patrick Morrow, Portland, OR (US);

Kimin Jun, Hillsboro, OR (US);

Il-Seok Son, Portland, OR (US);

Rajashree Baskaran, Seattle, WA (US);

Paul B. Fischer, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/8258 (2006.01); H01L 21/683 (2006.01); H01L 23/528 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 27/085 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0203 (2013.01); H01L 21/6835 (2013.01); H01L 21/8258 (2013.01); H01L 23/528 (2013.01); H01L 29/16 (2013.01); H01L 29/20 (2013.01); H01L 27/085 (2013.01); H01L 2221/68363 (2013.01);
Abstract

An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.


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