The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2019
Filed:
Feb. 20, 2018
Applicant:
Globalfoundries, Inc., Grand Cayman, KY;
Inventors:
Ruilong Xie, Niskayuna, NY (US);
Julien Frougier, Albany, NY (US);
Hiroaki Niimi, Cohoes, NY (US);
Nigel Cave, Saratoga Springs, NY (US);
Xusheng Kevin Wu, Hopewell Junction, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823835 (2013.01); H01L 21/02532 (2013.01); H01L 21/32139 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/66545 (2013.01);
Abstract
At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising dual silicides in contacts to FinFETs. The semiconductor device may comprise a PFET fin; an NFET fin; a first metal silicide around the NFET fin; a second metal silicide around the PFET fin; and a fill metal around the second metal silicide, above the PFET fin, and above the NFET fin. Methods of forming such devices are also disclosed.