The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Aug. 04, 2017
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Gary F. Besinga, Boise, ID (US);

Peng Fei, Shanghai, CN;

Michael G. Miller, Boise, ID (US);

Roland J. Awusie, Boise, ID (US);

Kishore Kumar Muchherla, Fremont, CA (US);

Renato C. Padilla, Folsom, CA (US);

Harish R. Singidi, Fremont, CA (US);

Jung Sheng Hoei, Newark, CA (US);

Gianni S. Alsasua, Rancho Cordova, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/28 (2006.01);
U.S. Cl.
CPC ...
G11C 16/28 (2013.01);
Abstract

Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.


Find Patent Forward Citations

Loading…