The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2019
Filed:
Feb. 19, 2018
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chih-Liang Chen, Hsinchu, TW;
Chih-Ming Lai, Hsinchu, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Chi-Yeh Yu, Hsinchu, TW;
Jiann-Tyng Tzeng, Hsin Chu, TW;
Kam-Tou Sio, Zhubei, TW;
Pin-Dai Sue, Tainan, TW;
Ru-Gun Liu, Zhubei, TW;
Shih-Wei Peng, Hsinchu, TW;
Wen-Hao Chen, Hsinchu, TW;
Yung-Sung Yen, New Taipei, TW;
Chun-Kuang Chen, Guanxi Township, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming gate structures and middle-end-of-the-line (MEOL) structures extending in a first direction over an active area of a substrate. The MEOL structures are interleaved between the gate structures along a second direction. The method further forms a power rail and a first metal wire extending in the second direction. The first metal wire is over the MEOL structures. A double patterning process is performed to form second and third metal wires extending in the first direction over the first metal wire and separated in the second direction. The second metal wire is cut according to a first cut region of a first cut mask to define a first metal strap connecting a first one of the MEOL structures to the power rail.