The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2019
Filed:
Nov. 16, 2015
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Kam-Tou Sio, Hsinchu County, TW;
Tsung-Yao Wen, Hsinchu, TW;
Chih-Ming Lai, Hsinchu, TW;
Hui-Ting Yang, Hsinchu County, TW;
Jui-Yao Lai, Changhwa, TW;
Chih-Liang Chen, Hsinchu, TW;
Chun-Kuang Chen, Hsinchu County, TW;
Ru-Gun Liu, Hsinchu County, TW;
Yen-Ming Chen, Hsinchu County, TW;
Chew-Yuen Young, Cupertino, CA (US);
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A layout modification method is performed by at least one processor. The layout modification method includes: analyzing, by the at least one processor, allocation of a plurality of specific layout segments of a circuit cell layout to determine a first specific layout segment and a second specific layout segment from the plurality of specific layout segments; determining, by the at least one processor, if the first specific layout segment and the second specific layout segment are coupled to a first signal level; and merging, by the at least one processor, the first specific layout segment and the second specific layout segment into a first merged layout segment when the first specific layout segment and the second specific layout segment are coupled to the first signal level.