The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Nov. 21, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Georgios Vellianitis, Heverlee, BE;

Mark van Dal, Linden, BE;

Blandine Duriez, Brussels, BE;

Richard Kenneth Oxland, Brussels, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/36 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 21/76224 (2013.01); H01L 21/76232 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/36 (2013.01); H01L 29/4236 (2013.01); H01L 29/6681 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.


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