The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jun. 22, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Martin Christopher Holland, Bertem, BE;

Georgios Vellianitis, Heverlee, BE;

Richard Kenneth Oxland, Brussels, BE;

Krishna Kumar Bhuwalka, Asansol, IN;

Gerben Doornbos, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/205 (2013.01); H01L 21/02538 (2013.01); H01L 29/1054 (2013.01); H01L 29/20 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7787 (2013.01); H01L 29/785 (2013.01);
Abstract

Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.


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