The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Apr. 26, 2017
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Sameer S. Vadhavkar, Boise, ID (US);

Xiao Li, Boise, ID (US);

Steven K. Groothuis, Boise, ID (US);

Jian Li, Boise, ID (US);

Jaspreet S. Gandhi, Boise, ID (US);

James M. Derderian, Boise, ID (US);

David R. Hembree, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/52 (2006.01); H01L 21/54 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/44 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2006.01); H01L 23/053 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01);
U.S. Cl.
CPC ...
H01L 23/44 (2013.01); H01L 21/52 (2013.01); H01L 21/54 (2013.01); H01L 21/563 (2013.01); H01L 23/053 (2013.01); H01L 23/3128 (2013.01); H01L 23/3675 (2013.01); H01L 23/3736 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/83104 (2013.01); H01L 2924/16235 (2013.01); H01L 2924/16251 (2013.01); H01L 2924/1815 (2013.01);
Abstract

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.


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