The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Oct. 04, 2016
Applicant:

Globalfoundries Inc., Grand Caymen, KY;

Inventors:

Ryan Ryoung-Han Kim, Bertem, BE;

Wenhui Wang, Santa Clara, CA (US);

Azat Latypov, San Jose, CA (US);

Tamer Coskun, Jr., San Jose, CA (US);

Lei Sun, Albany, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/306 (2006.01); H01L 21/8234 (2006.01); H01L 21/027 (2006.01); H01L 21/033 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0276 (2013.01); H01L 21/0337 (2013.01); H01L 21/3086 (2013.01); H01L 21/30604 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 22/12 (2013.01); H01L 22/30 (2013.01);
Abstract

Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.


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