The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

May. 21, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Richard F. Indyk, Wappingers Falls, NY (US);

Deepika Priyadarshini, Guilderland, NY (US);

Spyridon Skordas, Wappingers Falls, NY (US);

Edmund J. Sprogis, Williston, VT (US);

Anthony K. Stamper, Williston, VT (US);

Kevin R. Winstel, East Greenbush, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); B32B 3/02 (2006.01); B32B 3/30 (2006.01); B32B 7/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02035 (2013.01); B32B 3/02 (2013.01); B32B 3/30 (2013.01); B32B 7/12 (2013.01); H01L 21/02013 (2013.01); H01L 21/02021 (2013.01); B32B 2250/02 (2013.01); B32B 2457/14 (2013.01);
Abstract

Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.


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