The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Feb. 08, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ker Hsiao Huo, Zhubei, TW;

Chih-Chang Cheng, Hsinchu, TW;

Ru-Yi Su, Kouhu Township, TW;

Jen-Hao Yeh, Kaohsiung, TW;

Fu-Chih Yang, Fengshan, TW;

Chun Lin Tsai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 21/26 (2006.01); H01L 29/78 (2006.01); H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/265 (2013.01); H01L 29/0646 (2013.01); H01L 29/0696 (2013.01); H01L 29/1033 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/66325 (2013.01); H01L 29/66681 (2013.01); H01L 29/7393 (2013.01);
Abstract

An embodiment of a structure provides an enhanced performing high voltage device, configured as a lateral diffused MOS (HV LDMOS) formed in a tri-well structure (a small n-well in an extended p-type well inside an n-type well) within the substrate with an anti-punch through layer and a buried layer below the n-type well, which reduces substrate leakage current to almost zero. The drain region is separated into two regions, one within the small n-well and one contacting the outer n-type well such that the substrate is available for electric potential lines during when a high drain voltage is applied.


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