The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2018
Filed:
Jun. 10, 2016
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Ken-Hsien Hsieh, Taipei, TW;
Chih-Ming Lai, Hsinchu, TW;
Ru-Gun Liu, Hsinchu County, TW;
Wen-Chun Huang, Tainan, TW;
Wen-Li Cheng, Taipei, TW;
Pai-Wei Wan, Hsin-Chu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsin-Chu, TW;
Abstract
Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.