The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2018
Filed:
Apr. 03, 2017
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Cheng-Hsien Chou, Tainan, TW;
Sheng-Chau Chen, Tainan, TW;
Chun-Wei Chang, Tainan, TW;
Kai-Chun Hsu, Yonghe, TW;
Chih-Yu Lai, Tainan, TW;
Wei-Cheng Hsu, Kaohsiung, TW;
Hsiao-Hui Tseng, Tainan, TW;
Shih Pei Chou, Tainan, TW;
Shyh-Fann Ting, Tainan, TW;
Tzu-Hsuan Hsu, Kaohsiung, TW;
Ching-Chun Wang, Tainan, TW;
Yeur-Luen Tu, Taichung, TW;
Dun-Nian Yaung, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.