The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Jun. 20, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Su Xing, Singapore, SG;

Hsueh-Wen Wang, Hsinchu, TW;

Chien-Yu Ko, Tainan, TW;

Yu-Cheng Tung, Kaohsiung, TW;

Jen-Yu Wang, Tainan, TW;

Cheng-Tung Huang, Kaohsiung, TW;

Yu-Ming Lin, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 27/11585 (2017.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 21/28291 (2013.01); H01L 27/11585 (2013.01); H01L 29/6684 (2013.01); H01L 29/66545 (2013.01); H01L 29/7869 (2013.01);
Abstract

A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.


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