The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Sep. 16, 2016
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Ming Li, Singapore, SG;

Namchil Mun, Singapore, SG;

Jeoung Mo Koo, Singapore, SG;

Raj Verma Purakh, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0617 (2013.01); H01L 21/8238 (2013.01); H01L 27/092 (2013.01); H01L 29/063 (2013.01); H01L 29/1095 (2013.01); H01L 29/407 (2013.01); H01L 29/408 (2013.01); H01L 29/66681 (2013.01); H01L 29/66734 (2013.01); H01L 29/7809 (2013.01); H01L 29/7813 (2013.01); H01L 29/7816 (2013.01);
Abstract

VDMOS transistors, Bipolar-CMOS-DMOS (BCD) devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices are provided. In an example, a BCD device having a VDMOS transistor includes a buried layer over a substrate and an epitaxial layer over the buried layer and having an upper surface. Deep trench isolation regions extend from the upper surface of the epitaxial layer, into the substrate, and isolate a VDMOS region from a device region. In the VDMOS region, a source region is adjacent the upper surface, a vertical gate structure extends into the epitaxial layer, a body region is located adjacent the vertical gate structure and forms a channel, and a VDMOS conductive structure extends through the epitaxial layer and into the buried layer, which is a drain for the VDMOS transistor. The VDMOS conductive structure is a drain contact to the buried layer.


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