Jiangsu, China

Zhen Yao

This inventor holds 1 USPTO granted patent. Top assignee: Hc Semitek (Suzhou) Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Zhen Yao. Retrieved from https://idiyas.com/inventor/zhen-yao-k62of2re

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Zhen Yao: Advancing LED Epitaxial Wafer Technology

Introduction

Zhen Yao is an inventor based in Jiangsu, China, whose work includes a patented approach to manufacturing light-emitting diode (LED) epitaxial wafers and chips. His listed patent is associated with Hc Semitek (Suzhou) Co., Ltd. Yao is credited with 1 patent in the information provided.

Latest Patents

Yao’s patent, “Light-emitting diode epitaxial wafer, growth method therefor, and light-emitting diode chip,” describes a method for growing LED epitaxial structures on a sapphire substrate. The process forms indium-containing GaN crystal nuclei, then grows one or more composite layers made of InGaN and GaN sublayers. It subsequently adds an N-type GaN layer, an active layer, and a P-type GaN layer. The active layer contains alternating InGaN quantum wells and GaN quantum barriers.

The disclosed approach aims to form large, stable GaN crystal nuclei that help counteract stress caused by lattice mismatch between sapphire and GaN-based materials. This may support the growth of the epitaxial wafer structure used in an LED chip.

Career Highlights

The available information identifies Yao as an inventor associated with Hc Semitek (Suzhou) Co., Ltd. His listed patent focuses on LED epitaxial wafer growth and the structure of the resulting LED chip.

Collaborations

Ying Cong and Binzhong Dong are identified as Yao’s coworkers. The provided information does not specify their roles in the patent or describe particular joint projects.

Conclusion

Zhen Yao’s listed patent addresses LED manufacturing through a growth method designed to manage lattice-mismatch stress in GaN-based epitaxial structures.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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