Scarborough, ME, United States of America

Zailong Zhuang

This inventor holds 2 USPTO granted patents. Top assignee: Agere Systems Inc.. Active years: 2009-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Zailong Zhuang. Retrieved from https://idiyas.com/inventor/zailong-zhuang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.3

ph-index = 2

Forward Citations = 28(Granted Patents)


Location History:

  • Whitehall, PA (US) (2009)
  • Scarborough, ME (US) (2010)

Company Filing History:


Years Active: 2009-2010

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2 patents (USPTO):Explore Patents

Title: The Innovations of Zailong Zhuang

Introduction

Zailong Zhuang is a notable inventor based in Scarborough, ME (US). He has made significant contributions to the field of analog-to-digital conversion technology. With a total of 2 patents, Zailong has demonstrated his expertise and innovative spirit in his work.

Latest Patents

Zailong Zhuang's latest patents include a two-step sub-ranging analog-to-digital converter and a method for performing two-step sub-ranging in an analog-to-digital converter. This two-step ADC achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging, and FADC conversion without increasing the chip area or power consumption. The ADC utilizes interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in a ping-pong fashion, ensuring that both circuits are converting during every clock period. These advancements are accomplished without increasing the potential sources of bit decision mismatches in the two-step sub-ranging ADC.

Another significant patent is the phase-locked loop using multi-phase feedback signals. This invention features a signal generator, such as a fractional-N PLL, which includes a divider, a phase circuit, and a fractional accumulator in its feedback signal path. The divider control signal regulates the divisor value applied by the divider. In one embodiment, a phase selector chooses one of several phase-shifted output signals generated by the PLL's main signal path, while in another embodiment, the divider generates a divided signal from one of the phase-shifted output signals. A phase mixer then generates multiple phase-shifted divided signals and selects one as the PLL's feedback signal based on the phase-circuit signal.

Career Highlights

Zailong Zhuang is currently employed at Agere Systems Inc., where he continues to innovate and develop cutting-edge technologies. His work has had a significant impact on the field of electronics and signal processing.

Collaborations

Zailong has collaborated with Robert H. Leonowich, further enhancing the innovative projects they have undertaken together.

Conclusion

Zailong Zhuang's contributions to the field of analog-to-digital conversion and signal processing highlight his role as a leading inventor. His patents reflect a

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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