Phase-locked loop using multi-phase feedback signals

Abstract

A signal generator, such as a fractional-N PLL, has, in its feedback signal path, a divider, a phase circuit, and a fractional accumulator that generates control signals for the divider and the phase circuit. The divider control signal controls the divisor value applied by the divider. In one embodiment, a phase selector selects, based on the phase-circuit control signal, one of a plurality of phase-shifted output signals generated by the PLL's main signal path (e.g., by a multi-phase VCO) and the divider generates the feedback signal for the PLL from the selected signal. In another embodiment, the divider generates a divided signal from one of the phase-shifted output signals, and a phase mixer generates, from the divided signal, a plurality of phase-shifted divided signals and selects, based on the phase-circuit signal, one of the phase-shifted divided signals as the PLL's feedback signal.