Hsinchu, Taiwan

Yun-Ting Chiang

This inventor holds 1 USPTO granted patent and 4 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yun-Ting Chiang. Retrieved from https://idiyas.com/inventor/yun-ting-chiang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Yun-Ting Chiang: Semiconductor Device Innovation

Introduction

Yun-Ting Chiang is an inventor based in Hsinchu, Taiwan, and works at Taiwan Semiconductor Manufacturing Co., Ltd. His patent work includes semiconductor device fabrication, with a focus on processes for forming and cleaning structures used in advanced transistor devices.

Latest Patents

Chiang is associated with 1 patent: “Semiconductor Device and Method.” The invention describes forming a multilayer stack of alternating sacrificial and channel layers over a semiconductor substrate, then creating a dummy gate and sidewall spacers. An epitaxial source/drain region is grown through the stack, followed by formation of a metal-semiconductor alloy region and a coating layer. Because residual material can form on the spacer sidewalls during these steps, the method uses a wet-clean process to selectively remove it.

Career Highlights

Chiang’s listed patent reflects work on semiconductor manufacturing methods that address material formation and cleaning during device fabrication. The disclosed process aims to remove residual material from spacer sidewalls while preserving the surrounding structures.

Collaborations

The provided information lists Yao-Wen Hsu and Chun-Cheng Chou as Chiang’s coworkers. Their names are included here as professional associations; no specific roles in the patent are provided.

Conclusion

Yun-Ting Chiang’s patent contribution centers on a semiconductor fabrication method that combines multilayer channel structures, source/drain formation, alloy and coating steps, and selective wet cleaning.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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