The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Sep. 08, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yao-Wen Hsu, New Taipei, TW;

Yun-Ting Chiang, Hsinchu, TW;

Chun-Cheng Chou, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 70/00 (2026.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10P 70/27 (2026.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 64/251 (2025.01); H10D 64/62 (2025.01); H10D 84/0153 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0179 (2025.01); H10D 84/038 (2025.01); H10D 84/852 (2025.01);
Abstract

A method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers, forming a dummy gate stack over a top surface and sidewalls of the multi-layer stack, forming first spacers on sidewalls of the dummy gate stack, growing an epitaxial source/drain region that extends through the plurality of sacrificial layers and the plurality of channel layers, forming a metal-semiconductor alloy region on first portions of the epitaxial source/drain region, forming a coating layer on the metal-semiconductor alloy region, wherein during the forming of the metal-semiconductor alloy region and the coating layer, a residual layer is formed on sidewalls of the first spacers, and performing a wet clean process to selectively etch the residual layer from the sidewalls of the first spacers.


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Hsu, Yao-Wen. (2026). Semiconductor device and method (U.S. Patent No. 12721081). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12721081

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