Jiangsu, China

Yulong Ren

This inventor holds 1 USPTO granted patent. Top assignees: National Center for Advanced Packaging Co., Ltd., Shanghai Xianfang Semiconductor Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yulong Ren. Retrieved from https://idiyas.com/inventor/yulong-ren-8vwf67m1

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Yulong Ren and Sensing Chip Packaging Innovation.

Introduction

Yulong Ren is an inventor associated with Jiangsu, China. His work includes a patent for a sensing chip packaging structure and method, addressing a technical challenge in packaging chips that need to receive sensing signals.

Latest Patents

Ren’s listed patent, “Sensing Chip Packaging Structure and Method,” describes a package containing a substrate, a silicon interposer, and multiple chips, including sensing and non-sensing chips. The non-sensing chips are encapsulated in molding compound, while the sensing chips remain exposed.

The method places a protective cover above each sensing chip before molding the front side of the chips. After molding, the top of the protective cover is ground away. This approach is intended to prevent molding compound from blocking sensing signals and to support effective packaging of sensing chips. Ren is credited with 1 patent in the information provided.

Career Highlights

The supplied career information associates Ren with National Center for Advanced Packaging Co., Ltd. and Shanghai Xianfang Semiconductor Co., Ltd. These affiliations place his work in the semiconductor packaging field.

Collaborations

Peng Sun and Liqiang Cao are identified as Ren’s coworkers. The available information does not specify their roles in the patent or the extent of their collaboration.

Conclusion

Yulong Ren’s listed patent presents a packaging approach designed to protect sensing-chip functionality while encapsulating other chips, reflecting a focused contribution to semiconductor packaging technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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