Kanagawa, Japan

Yuko Nagaya

This inventor holds 1 USPTO granted patent. Top assignee: Renesas Electronics Corporation. Active years: 2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yuko Nagaya. Retrieved from https://idiyas.com/inventor/yuko-nagaya

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1


Company Filing History:


Years Active: 2011

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1 patent (USPTO):Explore Patents

Title: Yuko Nagaya: Innovator in Semiconductor Design

Introduction

Yuko Nagaya is a prominent inventor based in Kanagawa, Japan. She has made significant contributions to the field of semiconductor design, showcasing her expertise through her innovative patent.

Latest Patents

Yuko Nagaya holds a patent titled "Method of Designing Semiconductor Device." This patent outlines a method that includes dividing a layout region of a semiconductor chip into a matrix by a unit region. It also details the determination of an interconnection layout such that the occupation ratio of a high-density region to the layout region is less than 50%. The high-density region is defined as a set of unit regions where the interconnection density exceeds a predetermined reference value. This innovative approach enhances the efficiency and effectiveness of semiconductor device design.

Career Highlights

Yuko Nagaya is currently employed at Renesas Electronics Corporation, a leading company in the semiconductor industry. Her work at Renesas has allowed her to apply her innovative ideas and contribute to the advancement of semiconductor technology.

Collaborations

Yuko collaborates with Takashi Ueda, a fellow innovator in the field. Their partnership exemplifies the importance of teamwork in driving technological advancements.

Conclusion

Yuko Nagaya's contributions to semiconductor design through her innovative patent demonstrate her significant role in the industry. Her work continues to influence the development of efficient semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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