The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
May. 15, 2007
Applicants:
Takashi Ueda, Kanagawa, JP;
Yuko Nagaya, Kanagawa, JP;
Inventors:
Takashi Ueda, Kanagawa, JP;
Yuko Nagaya, Kanagawa, JP;
Assignee:
Renesas Electronics Corporation, Kawasaki, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method of designing a semiconductor device includes: (A) dividing a layout region of a semiconductor chip into matrix by a unit region; and (B) determining an interconnection layout such that an occupation ratio of a high-density region to the layout region is less than 50%. Here, the high-density region is a set of the unit regions in each of which interconnection density is higher than a predetermined reference value.
Ueda, Takashi. (2011). Method of designing semiconductor device (U.S. Patent No. 7890918). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7890918
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile