Tokyo, Japan

Yuji Enari

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Renesas Electronics Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yuji Enari. Retrieved from https://idiyas.com/inventor/yuji-enari

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Yuji Enari: Innovator in Semiconductor Technology

Introduction

Yuji Enari is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the field of semiconductor technology. His innovative work has led to the development of a unique semiconductor device and its manufacturing method.

Latest Patents

Yuji Enari holds 1 patent for his invention titled "Semiconductor device and method of manufacturing the same." This patent describes a process where an interlayer insulating film is formed on the upper surface of a semiconductor substrate. The invention includes the formation of a source pad, a kelvin pad, a gate pad, and a drain pad, each with a smaller plane area than the source pad. Additionally, a first plating layer is created on the source pad, while a second plating layer is formed on the other pads. The materials used in these layers are specifically chosen to enhance the device's performance.

Career Highlights

Yuji Enari is currently associated with Renesas Electronics Corporation, a leading company in the semiconductor industry. His role at the company allows him to further his research and development efforts in semiconductor technologies.

Collaborations

Due to space constraints, the collaborations section has been omitted.

Conclusion

Yuji Enari's contributions to semiconductor technology exemplify the innovative spirit of modern inventors. His patent reflects a significant advancement in the manufacturing of semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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