San Jose, CA, United States of America

Yufeng Jiang

This inventor holds 1 USPTO granted patent. Top assignee: Applied Materials, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yufeng Jiang. Retrieved from https://idiyas.com/inventor/yufeng-jiang-thoobnwc

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Yufeng Jiang and Semiconductor Deposition Innovation.

Introduction

Yufeng Jiang is an inventor based in San Jose, California, whose patent work addresses materials and processes used in semiconductor manufacturing. His disclosed invention concerns doped silicon oxide and bottom-up deposition within patterned features.

Latest Patents

Jiang is associated with 1 patent, titled “Doped Silicon Oxide for Bottom-Up Deposition.” The patent describes a process in which deposition precursors are introduced into a semiconductor processing chamber and plasma effluents are formed from those precursors. The effluents contact a substrate containing features with sidewalls, depositing a doped silicon-and-oxygen-containing material. The described process produces material on the feature sidewalls with poorer film quality than material deposited in the lower portions of the features, supporting bottom-up deposition.

Career Highlights

Jiang is associated with Applied Materials, Inc., a company that develops equipment and technologies for semiconductor manufacturing. His patent reflects work on deposition processes and material behavior within small, structured features.

Collaborations

Jiang’s listed coworker is Woongsik Nam. Their association provides context for the collaborative environment connected with the patent, although the supplied information does not specify their individual contributions.

Conclusion

Yufeng Jiang’s patent focuses on doped silicon oxide deposition and film-quality differences within semiconductor features, highlighting a specialized contribution to semiconductor processing technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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