Tainan, Taiwan

Yueh-Chang Lin

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: United Microelectronics Corp.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yueh-Chang Lin. Retrieved from https://idiyas.com/inventor/yueh-chang-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Yueh-Chang Lin: Innovator in Semiconductor Technology

Introduction

Yueh-Chang Lin is an inventor based in Tainan City, Taiwan. He has made significant contributions to the field of semiconductor technology. Although he currently holds no granted patents, his work in developing innovative semiconductor structures is noteworthy.

Latest Patent Applications

Yueh-Chang Lin's latest patent applications include:

1. **SEMICONDUCTOR STRUCTURE WITH FLUSH SHALLOW TRENCH ISOLATION AND GATE OXIDE AND METHOD OF MANUFACTURING THE SAME** - This application describes a method for manufacturing a semiconductor structure that features flush shallow trench isolation and gate oxide. The process involves multiple etching steps to create a gate oxide layer on a recessed substrate, ensuring that the top plane of the shallow trench isolation is flush with the gate oxide layer.

2. **SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF** - This application outlines a semiconductor structure that includes a substrate with two device regions. It details the design of a trench isolation structure that maintains specific height relationships between the device regions, enhancing the performance of the semiconductor device.

Conclusion

Yueh-Chang Lin's innovative approaches in semiconductor technology highlight his potential impact on the industry. His latest patent applications reflect a commitment to advancing semiconductor manufacturing techniques.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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