Hsinchu, Taiwan

Yu-Hsin Tseng

This inventor holds 3 USPTO granted patents. Top assignee: Faraday Technology Corporation. Active years: 2010-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yu-Hsin Tseng. Retrieved from https://idiyas.com/inventor/yu-hsin-tseng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 66.7

Average Co-Inventor Count = 1.7

ph-index = 2

Forward Citations = 8(Granted Patents)


Company Filing History:


Years Active: 2010-2023

Loading Chart...
3 patents (USPTO):Explore Patents

Title: Innovations of Yu-Hsin Tseng

Introduction

Yu-Hsin Tseng is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of electronics, particularly in clock data calibration and recovery circuits. With a total of 3 patents to his name, Tseng continues to push the boundaries of innovation in his industry.

Latest Patents

One of Yu-Hsin Tseng's latest patents is a clock data calibration circuit. This circuit includes a first comparator, a multi-phase clock generator, a plurality of samplers, a plurality of data comparators, and a data selector. The first comparator compares first input data with second input data to generate a data signal. The multi-phase clock generator generates a plurality of clock signals, which are divided into several clock groups. The sampler samples the data signal according to the clock groups to generate multiple first sampled data signal groups. The data comparators sample these first sampled data signal groups according to selected clocks to produce several second sampled data signal groups. Each data comparator generates status flags based on the variation state of the second sampled data. The data selector then generates output data signals according to these status flags.

Another significant patent by Tseng is a clock data recovery circuit. This circuit comprises a phase blender, a phase detector, a data sampling position detector, and a data selector. The phase blender generates a third and a fourth clock signal based on a first and second clock signal. The phase detector samples a data signal according to the first and second clock signals, producing first sampled data, second sampled data, and a phase state signal. The data sampling position detector samples the data signal using the third and fourth clock signals to generate third and fourth sampled data along with a control signal. Finally, the data selector generates output data based on the control signal and the phase state signal.

Career Highlights

Yu-Hsin Tseng is currently employed at Faraday Technology Corporation, where he applies his expertise in electronic circuit design. His work has been instrumental in advancing the company's technological capabilities and product offerings.

Collaborations

Tseng collaborates with talented individuals such as Jing-Zhi Gao and Wen-Ching Hsiung, who contribute to the innovative projects at Faraday Technology Corporation.

Conclusion

Yu-Hsin Tseng is a prominent inventor whose work in clock data calibration and recovery circuits has

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…