This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2026
Title: Yu-Chian Chiang and Integrated Circuit Packaging
Introduction
Yu-Chian Chiang is an inventor based in Kaohsiung, Taiwan. His work includes an invention concerning integrated circuit packages and methods for forming them. He is associated with Taiwan Semiconductor Manufacturing Co., Ltd.
Latest Patents
Chiang is credited with 1 patent: “Integrated Circuit Packages and Methods.” The patent describes an integrated circuit package that may include a die with a substrate and a through via, a gap-fill layer along the substrate’s sidewall, and an isolation layer extending across the interface between them and along the through via’s sidewalls. A bonding layer and bonding pad are formed over the isolation layer. The disclosed method addresses the formation of this package structure.
Career Highlights
Chiang’s listed patent reflects work in semiconductor packaging, particularly the arrangement of substrate, gap-fill, isolation, and bonding components in an integrated circuit package. His company affiliation connects this work with Taiwan Semiconductor Manufacturing Co., Ltd.
Collaborations
The provided information lists Yi-Hsiu Chen and Chia-Fang Tsai as Chiang’s coworkers. It does not specify their roles in the patent or whether they collaborated on this invention.
Conclusion
Yu-Chian Chiang’s patent focuses on an integrated circuit package structure and its formation, highlighting his contribution to semiconductor packaging innovation.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile